This invention relates to method and apparatus for converting a software representation of a first data storage circuit having a first type of input signals into an equivalent software representation of a second data storage circuit having a second type of input signals. In particular, the invention provides both hardware and software for implementing a macrocell with a storage device having both asynchronous clear and asynchronous load inputs based on design data being supplied for a different device, one in which the inputs for a data storage device are asynchronous clear and asynchronous preset.
Programmable logic devices combine the advantages of standard, mass producible integrated circuits with the architectural flexibility of custom devices. Altera Corporation manufactures programmable logic devices which provide user-configurable input/output pins, programmable configurability, and clock options that ensure maximum flexibility for integrating random logic functions. The fundamental building block of an Altera programmable logic device is the macrocell.
FIG. 1 illustrates a standard macrocell used in some of the MAX product line devices manufactured by Altera. Although this is one example of a macrocell, it will be apparent that many other macrocells could be used having similar or dissimilar structures. The macrocell 100 consists of a logic array 110, a programmable register (or flip-flop) 112, and programmable input/output connections 114. The programmable register may be programmed to provide a conventional D, T, JK or SR function. The register 112 has an asynchronous clear and asynchronous preset capability that allows complete emulation of many TTL functions. Other commercially available programmable logic devices incorporate similar macrocells and registers.
FIG. 2 illustrates a macrocell 200 used in the Altera FLEX programmable logic device. The Altera Flex programmable logic is an SRAM-based programmable logic device more fully described in commonly assigned pending application Ser. No. 880,942, filed May 8, 1992, now U.S. Pat. No. 5,260,611. Unlike the previously described macrocells, the Altera Flex macrocell 200 does not include an asynchronous preset input. Instead, the macrocell 200 is implemented using a programmable register 210 having asynchronous clear 212 and asynchronous load 214 inputs. An advantage of using an asynchronous load input instead of an asynchronous preset input is that a group of macrocells may share a common load signal. If a design requires asynchronously loading a group of registers having only clear and preset inputs, unique logic must be created for every similarly configured register. A dedicated load line allows this function to be performed without adding extra combinatorial logic for each register.
FIGS. 3 and 4 are the function tables corresponding to the programmable registers shown in FIGS. 1 and 2 respectively. The table shown in FIG. 3 is for a programmable flip-flop having active high clear and preset signals as inputs. The table shown in FIG. 4 is for a programmable flip-flop having active high clear and asynchronous load inputs. In both FIGS. 3 and 4, Q.sub.n is the output of the flip-flop prior to the clock transition and Q.sub.n+1 is the output of the flip-flop after the clock transition.
Although the asynchronous clear/asynchronous load macrocell offers the advantage of a common load signal, many engineers and logic designers are not familiar with macrocells whose programmable registers do not include both asynchronous clear and asynchronous preset inputs. An engineer not familiar with an asynchronous clear/asynchronous load macrocell may find designing programmable logic using this alternative macrocell frustrating. Thus, a method and apparatus is needed whereby a hardware designer or user of programmable logic can design products using logic which includes storage devices having asynchronous clear and asynchronous preset inputs, but which logic is readily transferrable to a circuit using storage devices having asynchronous clear and asynchronous load inputs. The designer should be able to specify register inputs and interconnections based on a standard asynchronous clear/asynchronous preset type storage device. The method and apparatus for creating an equivalent storage device should be transparent to the user to avoid user frustration.